So after getting working single PHY IC on new revision of OpenWrt driven SoM we continue development process to get working two PHY IC on same PCB.
First of all we soldered second testbench that provides access to core functionality (JTAG, both ethernet interfaces and UART console) of SoM module:
One of the testbench loaded with SoM having both PHY IC soldered. Another testbench loaded with single PHY IC soldered SoM module.
At least we have working link under U-boot so we can update firmware of device via TFTP.
As you remember we got working single PHY IC and was reading registers value using u-boot’s mii command. A similar command was sorely lacking under Linux. So we started with searching any utilitiy giving same functionality under Linux and found it here.
Step 3. Adding phytool package.
Clone project and create phytool package folder:
as expected proper PHY registers value on SoM with single PHY IC:
Step 4. DTS modification.
fec1 node presents Fast Ethernet Controller
mdio presents mdio serial interface used for communication between MAC controller (MCU) and PHY IC for configuration purposes. Currently single IC exist on that bus presented by ethphy0 node with address 0. Address of KSZ8081 must be implemended on circuit design stage. Table 2-2 at page 9 of datasheet explains how it can be done.
Before adding second fec node existing one must be modified according to changes made in new PCB revision – specifically RESET pin GPIO connected to MCU:
phy-reset-duration and phy-reset-post-delay used to configure reset delay duration and duration of delay after reset in milliseconds. That values should be bigger that minimum applicable delays for specific IC described in datasheet for that IC.
phy-reset-gpios used to set specific GPIO of MCU connected to RST pin of PHY IC. LCD_DATA_13 in our case. GPIO_ACTIVE_LOW configures active signal level (LOW) to perform reset of PHY IC. E.g. reset pin should be driven LOW to perform a reset and remains HIGH in normal operation mode. LOW and HIGH are signal’s voltage levels – 0v and 3.3V.
LCD_DATA_13 pin of MCU must be configured as simple GPIO to drive reset pin of IC so gpio3 18 is number of that pin. All MCU gpios distributed to few GPIO controllers. Each of them controls up to 32 gpio. Exact gpio number of each MCU’s pad can be determined by following iomux map:
just find pad you interested in.
After that we need to add another on fec node describing second PHY IC:
It looks much simplier rather than fec1 node. No need to describe mdio bus as it is already described in fec1 (same MDIO bus shared between two PHY IC). LCD_DATA0 (gpio3 5) pad of MCU connected to reset pin of PHY IC. phy-handle pointed to ethphy1 node not existing in DTS yet so it should be added:
right after already existing ethphy0 node. Here reg = <3> determines PHY IC address on MDIO bus (Configurable PHY addresses are: 0h, 3h, 4h or 7h as explained in datasheet).
pinctrl-0 points to pinctrl_enet2 need to be implemented too:
pinctrl_enet2 should be placed right after pinctrl_enet1 node.
And the last one change – pinctrl_enet1 need to be modified by adding by adding two more pins describing MDIO bus used for communication with PHY ICs:
It might be confusing – where all this magic numbers and pad definitions taken from. As linux not well documented – the only way to understand it – research in existing source code base. I a case of DTS just search for already existing dts samples:
or commits modifying dts.
If you not sure about proper pad definition you might search for it in source code:
UPD. NetSoM released!
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