IMX6 Ethernet. Development process to add second ethernet PHY IC support. part 3.
In previous chapter we modified DTS to add support for second PHY IC on our IMX6 Ethernet equipped SoM. Time to test it. After compilation of image: $ ./compile.sh flexcan_wifi and updating device firmware: root@OpenWrt:/# scp user@host_address:/path_to_project/lorawan-imx6ull/bin/targets/imx6ull/cortexa7/openwrt-imx6ull-cortexa7-fl
IMX6 Ethernet. Development process to add second ethernet PHY IC support. part 2.
IMX6 Ethernet development process continuation. So after getting working single PHY IC on new revision of OpenWrt driven SoM we continue development process to get working two PHY IC on same PCB. First of all we soldered second testbench that provides access to core functionality (JTAG, both ethernet interfaces and UART console) of So
IMX6 Ethernet. Development process to add second ethernet PHY IC support. part 1.
In last (I hope) revision of OpenWrt driven SoM module we added second ethernet PHY IC to increase functionality of module. Here described IMX6 Ethernet support development process. Support for second ethernet PHY IC to be more precise. Changes made in hardware: shared MDIO interface between two PHY IC (KSZ8081RNAIA); RESET pin routed
SOM based architecture
Two years ago when we started development of LoRaWAN gateway the only starting point that was not in doubt was the decision to use OpenWrt OS. Another requirement was the need to use and industrial grade processor. After many hours of searching we were unable to find such processor we can buy as is and design our […]